Triple Input Sorter Optimization Algorithm of Median Filter Based on FPGA

This project is focused on developing hardware implementations of image processing algorithm for use in an FPGA -based image processing system, this approach facilitates comparison of the software and synthesized hardware algorithm outputs. The rank order filter is a particularly common algorithm in image processing systems. This approach was taken because it speeds understanding of the algorithm design, reduces the number of comparison, and the area required. For every pixel in an image, the window of neighbouring pixels is found. Then the pixel values are sorted in ascending, or rank, order. Next, the pixel in the output image corresponding to the origin pixel in the input image is replaced with the value specified by the filter order. The main advantage of the sorting network is that the sequence of comparisons is fixed. Thus it is suitable for parallel processing and hardware implementation, especially if the number of sorted elements is small. The number of compare–swap components and delay are two crucial parameters of any sorting network. By delay we mean the minimal number of groups of compare–swap components that must be executed sequentially. This algorithm ensures the number of comparators and delay used for given input and reduces the number of comparisons and computation time.